1. Field
Exemplary embodiments of the present invention relate to technology capable of controlling a buffer for receiving data of a channel when a high speed signal and a low speed signal are applied to one channel.
2. Description of the Related Art
Buffers are circuits that receive signals input to an integrated circuit chip. A buffer capable of receiving (recognizing) a signal input at a high speed (high frequency) generally consumes a large amount of current. However, a buffer capable of receiving a signal input at a low speed (low frequency) generally consumes a small amount of current.
A command and an address, which are low speed signals, or data, which is a high speed signal, may be applied to an I/O pin of a flash memory. If a high speed type buffer is used to receive a signal input to the I/O pin, a logic level of the signal may be normally recognized, but a large amount of current may be consumed. Furthermore, if a low speed type buffer is used to receive the signal applied to the I/O pin, current consumption may be reduced, but a logic level of a high speed input signal may not be recognized. In this regard, technology including the features of recognizing high and low speed data and reducing current consumption may be useful. All kinds of integrated circuits for receiving a high speed signal or a low speed signal to one pin may benefit from such useful features, including a flash memory.
FIG. 1A is a diagram illustrating an inverter-type buffer, which is one of low speed-type buffers, and FIG. 1B is a diagram illustrating an amplifier-type buffer, which is one of high speed-type buffers.
Referring to FIG. 1A, the inverter-type buffer includes PMOS transistors 101, 102, 104 and 105 and NMOS transistors 103, 106, and 107.
When an on/off signal ON/OFF is at a ‘low’ logic level, the PMOS transistors 101 and 104 are turned on, so that the inverter-type buffer is activated.
When the inverter-type buffer is activated and an input signal IN has a high logic level, the NMOS transistor 103 and the PMOS transistor 105 are turned on, so that an output signal OUT of the buffer is at a ‘high’ logic level. Meanwhile, when the input signal IN has a low logic level, the PMOS transistor 102 and the NMOS transistor 106 are turned on, so that the output signal OUT of the buffer is at a ‘low’ logic level. Since the inverter-type buffer consumes a current only when a signal is input, it consumes a small amount of current, but recognizing a logic value of a high speed input signal, more specifically, a signal having a small swing width, may be difficult for the inverter-type buffer. FIG. 1A illustrates the most basic inverter-type buffer. However, the inverter-type buffer may have various structures different from FIG. 1A.
Referring to FIG. 1B, the amplifier-type buffer has a differential amplifier structure that detects a potential difference between an input signal IN and a reference voltage VREF. Two PMOS transistors 108 and 109 form a current mirror structure, so that the same current is supplied to nodes A and B, and the two nodes A and B are differentially amplified by the potential difference between the reference voltage VREF input to the NMOS transistor 110 and the input signal input to the NMOS transistor 111. As a consequence, when the input signal IN has a voltage higher than that of the reference voltage VREF, an output signal OUT has a ‘high’ logic level, and when the input signal IN has a level voltage than that of the reference voltage VREF, the output signal OUT has a ‘low’ logic level. The NMOS transistor 112 receiving an on/off signal ON/OFF is turned on when the on/off signal ON/OFF is at a ‘high’ logic level. When the NMOS transistor 112 is turned on, the buffer is activated, and when the NMOS transistor 112 is turned off, the buffer is deactivated. As a consequence, the amplifier-type buffer is activated when the on/off signal ON/OFF is at the ‘high’ logic level.
Such an amplifier-type buffer may accurately recognize the logic value of a signal even when the input signal IN has a small swing width (more specifically, the input signal is applied at a high speed), but consumes a large amount of current while the buffer is being activated because a current flows through the buffer when a signal is not applied. FIG. 1B illustrates the most basic amplifier-type buffer. However, the amplifier-type buffer may have various structures different from FIG. 1B.